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FAN5068
DDR-1/DDR-2 plus ACPI Regulator Combo
Features
* PWM regulator for VDDQ (2.5V or 1.8V) * Linear LDO regulator generates VTT = VDDQ/2, 1.5A Peak sink/source capability * 1 independent programable ULDO controllers driving external N-Channel MOSFET * ACPI drive and control for 5V DUAL generation * 3.3V Internal LDO for 3V-ALW generation * 300kHz fixed frequency switching * RDS(ON) current sensing or optional current sense resistor for precision over-current detect * Internal Synchronous Boot diode * Power Good signal for all voltages * Input Under-Voltage Lock-Out (UVLO) * Thermal Shutdown * Latched Multi-Fault Protection * 24-pin 5x5mm MLP package
General Description
The FAN5068 DDR memory regulator combines a highefficiency PWM controller to generate the supply voltage, VDDQ, and a linear regulator to generate VTT, the termination voltage. Synchronous rectification provides highefficiency over a wide range of load currents. Efficiency is further enhanced by using the low-side MOSFET's RDS(ON) to sense current instead of a series sense resistor. In S3 mode, only the VDDQ switcher and the 3.3V regulators remain on while the VTT and ULDO regulators are shut off. To avoid "glitching" the VDDQ output during the transition from S3 to S0, the three linear regulators use the SS capacitor to limit their slew rates, thereby limiting the surge current from the VDDQ output. PGOOD becomes true in S0 only when all 3 regulators have achieved stable outputs. In S5 (EN = 0), the 3.3V internal LDO stays on, while the other regulators are powered down. The VDDQ PWM regulator is a sampled current mode control with external compensation to achieve fast load transient response and provide system design optimization. The VTT regulator derives its reference and takes its power from the VDDQ PWM regulator output using a precision internal voltage divider to set its output at 1/2 of VDDQ. The VTT termination regulator is capable of sourcing or sinking at least 1.5A peak current.
Applications
* DDR-1/DDR-2 VDDQ and VTT voltage generation with ACPI support * Desktop PC's * Servers
REV. 1.0.1 9/9/04
PRODUCT SPECIFICATION
FAN5068
Block Diagrams
5V DUAL +12 Q4 +5VSB C13 5V MAIN SBSW BOOT S3#O +5VSB VCC C4 EN S3#I C3 R5 SS ILIM PGOOD 3.3 MAIN VCC Q5 3.3 ALW VDDQ C12 Q6 1.2 OUT C17 R7 G1.2 FB1.2 R8 S3 SYS LDOs VTT LDO LDRV GND FB C9 COMP VDDQ IN REF IN VTT SNS VTT OUT C8 C7 C10 R10 R6 R1 C6 C11 R9 PWM ISNS HDRV SW R3 Q2 R2 L1 VDDQ COUT Q1 C2 C1 C5 L2 R4 Q3 +5MAIN
Figure 1. DDR/ACPI System Regulation Schematic
The components selected are for a 15A ouput on VDDQ.
Table 1. BOM for Figure 1
Description See notes below See notes below Capacitor 1uF, 10%, 16VDC, X7R, 1206 Capacitor 10nF, 10%, 100VDC, X7R, 0805 Capacitor 2.2nF, 10%, 50V, X7R, 0805 Capacitor 33pF, 10%, 50VDC, NPO, 0805 Capacitor 10nF, 10%, 100VDC, X7R, 0805 Capacitor 220nF, 20%, 10VDC, X5R, 0603 Capacitor 100nF, 10%, 25VDC, X7R, 0805 Inductor 1.8uH, 3.24m, 16 Amps, 20%, 0.5" Inductor 0.39uH, 2.8m, 15 Amps, 20%, 0.25" MOSFET N-CH, 8.8m, 30V, 50A, D-PAK, FSID: FDD6296 2
Qty
Ref. COUT C1, C12, C17
Vendor
Part Number
2 1 1 1 2 1 1 1 1 1
C2, C4 C3 C6 C9 C10, C11 C5 C8 L1 L2 Q1
KEMET Panasonic AVX Panasonic Panasonic AVX Kemet Inter-Technical Inter-Technical Fairchild
C1206C105K4RACTU ECJ-2VB2A103K 08055C222KAT2A ECJ-2VC1H330J ECJ-2VB2A103K 06033D224MAT C0805C104K3RACTU SC5018-1R8M SC7232-R39M FDD6296
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FAN5068
PRODUCT SPECIFICATION
Table 1. BOM for Figure 1 (continued)
Description MOSFET N-CH, 6m, 30V, 75A, D-PAK, FSID: FDD6606 MOSFET N-CH, 32m, 20V, 21A, D-PAK, FSID: FDD6530A MOSFET P-CH, 35m, -20V, -5.5A, SSOT-6, FSID: FDC602P Resistor 1.82k, 1%, 0805 Resistor 56k, 1%, 0805 Resistor 60.4k, 1%, 0805 Resistor 3.01k, 1%, 0603 Resistor 9.09k, 1%, 0603 Resistor 10k, 1%, 0805 Resistor 1k, 1%, 0805 IC System Regulator, MLP 24-Pin 5X5mm
Qty 1 3 1 4 1 1 1 1 1 1 1
Ref. Q2 Q3, Q6, Q5 Q4 R1, R2, R9, R10 R5 R6 R7 R8 R4 R3 U2
Vendor Fairchild Fairchild Fairchild Yageo Any Any
Part Number FDD6606 FDD6530A FDC602P 9C08052A1821FKHFT
Any Any Fairchild FAN5068
Bypass Capacitor Notes:
Input capacitor C1 is typically chosen based on the ripple current requirements. COUT is typically selected based on both current ripple rating and ESR requirement. See AN6006 for these calculations.
C17 and C12 selection will be largely determined by ESR and load transient response requirements. In each case, the number of capacitors required depends on the capacitor technology chosen. Oscons can meet the requirements with less space, but higher cost than using low ESR electrolytics (like Rubycon MBZ).
5V D2 BOOT CBOOT VIN Q1
EN S3
POR/UVLO
S3 HDRV OVP FB RAMP Q SR PWM
4.41K
SW
VDDQ Q2 L OUT COUT
ADAPTIVE GATE CONTROL LOGIC
PWM
VDD LDRV PGND
VIN
OSC
CLK
COMP FB
S/H RAMP
ILIM det. ISNS
ISNS
RSENSE
CURRENT PROCESSING
SS PGOOD
VDDQ IN
Reference and Soft Start
VREF ILIM R ILIM
Figure 2. PWM Modulator Block Diagram REV. 1.0.1 9/9/04
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PRODUCT SPECIFICATION
FAN5068
VDDQ IN S3 R9 REF IN 50K VDDQ IN
R10 EN
+
50K
VTT OUT
-
VTT SNS
PGND
Figure 3. VTT Regulator Block Diagram
Pin Configuration
REF IN COMP GND
19 18 17 16
24
23
22
21
20
G1.2 FB1.2 SBSW 5V MAIN VTT SNS VTT OUT
ILIM
SS
FB
1 2 3
EN S3#I S3#O 3.3 ALW VCC PGOOD
P1 = GND
4 5 6 7 8 9 10 11 12 15 14 13
HDRV
SW
ISNS
FAN5068MP 5x5 mm MLP-24 Package (JA = 38C/W, JC = 1.4C/W)* Note: Connect P1 pad to GND.
Pin Definitions
Pin # 1 2 3 4 5 6 7 Pin Name G1.2 FB1.2 SBSW 5V MAIN VTT SNS VTT OUT VDDQ IN Pin Function Description Gate Drive for the 1.2V LDO. Turned off (low) in S3 and S5 modes. Feedback for the 1.2V LDO Output. Tie to a voltage higher than 0.9V to disable this regulator. Standby Switch. Drives the P-Channel MOSFET to power 5V DUAL from 5VSB when in S3. Goes high in S0 and S5. 5V MAIN. When this pin is below 4.5V, transition from S3 to S0 is inhibited. VTT Remote Sense Input. VTT Regulator Power Output. VDDQ Input from PWM. Connect to PWM output voltage. This is the VTT Regulator power input.
*Test method as per JEDEC Specification JESD51-5
4
VDDQ IN
BOOT
LDRV
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PRODUCT SPECIFICATION
Pin Definitions (continued)
Pin # 8 9 10 11 12 13 Pin Name BOOT HDRV SW ISNS LDRV PGOOD Pin Function Description Boot. Positive supply for the upper MOSFET driver. Connect as shown in Figure 1. IC contains a boot diode to VCC. High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. Current Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET. Power Good Flag. An open-drain output that will pull LOW when FB is outside of a 10% range of the 0.9V reference and the LDO outputs are > 80% or < 110% of its reference. PGOOD goes low when S3 is high. The power good signal from the PWM regulator enables the VTT regulator and the LDO controller. VCC. The IC takes its bias power from this pin. Also used for gate drive power. The IC is held in standby until this pin is above 4.35V (UVLO threshold). 3.3V LDO Output. Internal LDO output. Turned off in S0, on in S5 or S3 modes. S3# Output. Open-drain output which pulls the gates of two N-Channel blocking MOSFETs low in S5 and S3. This pin goes high (open) in S0 mode. S3 Input. When LOW, turns off the VTT and 1.2V LDO regulators and turns on the 3.3V regulator. Also causes S3#O to pull low to turn off blocking switch Q3 as shown in Figure 1. PGOOD is low when S3#I is LOW. ENABLE. Typically tied to S5#. When this pin is low, the IC is in a low quiescent current state, all regulators are off and S3#O is low. GROUND for the IC are tied to this pin and also connected to P1. Current Limit. A resistor from this pin to GND sets the current limit. Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization as well as sets the initial slew rate of the LDO controllers when transitioning from S3 to S0. This pin is charged/discharged with a 5A current source during initialization, and charged with 50A during PWM soft-start. Output of the PWM error amplifier. Connect compensation network between this pin and FB. VDDQ Feedback. The feedback from PWM output. Used for regulation as well as PGOOD, under-voltage, and over-voltage protection and monitoring. VTT Reference. Input which provides the reference for the VTT regulator. A precision internal divider from VDDQ IN is provided.
14 15 16 17
VCC 3.3 ALW S3#O S3#I
18 19 20 21
EN GND ILIM SS
22 23 24
COMP FB REF IN
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PRODUCT SPECIFICATION
FAN5068
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Parameter VCC BOOT, SW, ISNS, HDRV, S3#O BOOT to SW All Other Pins Junction Temperature (TJ) Storage Temperature Lead Soldering Temperature, 10 seconds I(VTT) Peak (Duration < 2ms) I(VTT) RMS -0.3 -20 -65 Min. Typ. Max. 6.5 28 6.5 VCC+0.3 150 150 300 1.5 1 Units V V V V C C C A A
Recommended Operating Conditions
Parameter Supply Voltage VCC I(3.3 ALW) Ambient Temperature (TA) -10 Conditions Min. 4.5 Typ. 5 Max. 5.5 1.25 85 Units V A C
Electrical Specifications
Recommended operating conditions, component values per Figure 1 unless otherwise noted. Parameter Power Supplies VCC Current: S0 S3 S5 VCC UVLO Threshold LDRV, HDRV Open, FB forced above regulation point, I(VTT) = 0, EN = 1, S3#I = 1 EN = 1, S3#I = LOW, I(3.3) < 10mA EN = 0, I(3.3) = 0 Rising VCC Falling Hysteresis 5V MAIN UVLO Threshold Rising Falling Hysteresis Oscillator Frequency Ramp Amplitude, pk-pk Ramp Offset Reference and Soft Start Internal Reference Voltage Soft Start current (ISS) SS Discharge on-resistance Initial ramp after power-up During PWM / LDO soft start EN = 0 0.891 0.900 4.5 48 150 0.909 V A 255 300 1.8 0.5 345 kHz V V 4.3 3.9 4.0 3.9 15 15 2 4.2 4.05 0.150 4.4 4.1 0.300 4.6 4.2 24 24 4 4.4 4.2 mA mA mA V V V V V V Conditions Min. Typ. Max. Units
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PRODUCT SPECIFICATION
Electrical Specifications (continued) Recommended operating conditions, component values per Figure 1 unless otherwise noted.
Parameter SS Complete Threshold SS Complete Hysteresis PWM Converter Load Regulation FB Bias Current Under-Voltage Shutdown ISNS Over-Current threshold Over-Voltage threshold PWM Output Driver HDRV Output Resistance LDRV Output Resistance Sourcing Sinking Sourcing Sinking PGOOD (Power Good Output) and Control pins. VDDQ output Lower Threshold Upper Threshold PGOOD Output Low Leakage Current VTT Regulator VDDQ IN Current VREF IN to VTT Differential Output Voltage Internal Divider Gain VTT Current limit VTT Leakage Current VTT SNS input resistance VTT PGOOD Drop-Out Voltage 1.2V LDO Regulation Drop-Out Voltage External Gate Drive Gate Drive Source Current Gate Drive Sink Current External Gate Drive FB1.2 PGOOD threshold 3.3V LDO Regulation Drop-Out Voltage I(3.3) from 0 to 1.25A, VCC > 4.75V I(3.3) 1.25A 3.2 3.3 3.4 1.5 V V VCC = 4.75V I(1.2) from 0 to 5A I(1.2) 5A, RDS(ON) < 50m VCC = 4.75V 1.2 1.2 4.5 0.80 1.17 1.2 1.23 0.3 4.5 V V V mA mA V V Pulsed (300ms max.), TA = 25C S3#I = LOW VTT = 0.9V Measured at VTT SNS ITT = 1.5A 80 -0.8 S0 mode, IVTT = 0 IVTT = 0, TA = 25C IVTT = 1.25A (pulsed) -20 -40 0.493 1.5 -20 110 110 0.8 0.498 3 35 70 20 40 0.503 4 20 mA mV V/V A mA k % VTT REF V As % of set point, 2s noise filter As % of set point, 2s noise filter IPGOOD = 1.5mA VPULLUP = 5V 86 108 92 115 0.5 1 % % V A 1.8 1.8 1.8 1.2 3 3 3 2 As % of set point. 2s noise filter RILIM = 56k As % of set point IOUT from 0 to 16A -2 0.75 65 145 110 1 75 170 115 +2 1.25 80 195 120 % A % A % Conditions Min. Typ. 1.5 50 Max. Units V mV
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PRODUCT SPECIFICATION
FAN5068
Electrical Specifications (continued) Recommended operating conditions, component values per Figure 1 unless otherwise noted.
Parameter Control Functions S3#I, EN Input Threshold S3#I EN Input Current Over-Temperature Shutdown Over-Temperature Hysteresis S3#O Output Low RDS(ON) S3#O Output High Leakage SBSW Output Low Resistance SBSW Sink current (note 1) SBSW Output High (note 2) V(S3#O) = 12V 5V MAIN OK 5V MAIN < UVLO 1.0 -1 150 25 170 4 125 500 820 1200 300 10 200 1.25 1.55 1 V A C C A nA Conditions Min. Typ. Max. Units
Circuit Description
Overview
The FAN5068 provides 5 functions: 1. 2. 3. A general purpose PWM regulator, typically used to generate VDDQ for DDR memory. A low-dropout linear VTT regulator capable of sinking and sourcing 1.5A peak. An adjustable Ultra Low Drop Out (ULDO) controller which, in conjunction with an external N-Channel power MOSFET, provides a programmable low voltage output. The power source for this output is typically the VDDQ output and is used to provide the 1.2V GTL processor FSB termination voltage. 5. 4. Control for generating a 5V DUAL voltage using an external N-channel to supply power from 5V MAIN in S0, and an external P-Channel to provide power from 5V Standby (5VSB) in S3. An internal LDO which regulates "3.3V Always" in S3 mode from VCC(VSB). In S3, this regulator is capable of 1.25A peak currents with average currents limited by the thermal design of the PCB.
At initial power-up, or when transitioning from S5, the PWM regulator will be disabled until 5V MAIN is above its UVLO threshold.
Table 2. ACPI States
STATE S5 S3 S0
S3#I X L H
EN (S5#) L H H
S3#O L L H STATE S5 S3 S0
SBSW H L H 3.3 ALW LDO LDO Q5 (MAIN)
VDDQ OFF ON ON
VTT OFF OFF ON
G1.2 LDO 3.3 ALW LDO OFF OFF ON ON ON OFF
5V Dual OFF +5VSB +5 MAIN
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FAN5068
PRODUCT SPECIFICATION
Regulator Sequencing
The VCC pin provides power to all logic and analog control functions of the regulator including: 1. 2. 3. 4. Power for the 3.3V regulator LDRV gate driver current HDRV boot diode charging current. The regulator analog control and logic
In most systems, the ATX power supply is enabled when S3#I goes from high. At that point, 5V and 3.3V MAIN will start to rise. The FAN5068 waits until 5V MAIN is above 4.5V to turn on Q3 and Q5. This can cause about a 10% "bump" in both 5V DUAL and 3.3V ALW when Q3 and Q5 turn on, since at that point, 5V MAIN and 3.3V MAIN are at 90% of their regulation value.
5V DUAL
This pin must be decoupled with a ceramic capacitor (4.7F or larger recommended) as close as possible to the VCC pin. After VCC is above UVLO, the start-up sequence begins as shown in Figure 6. T1 to T3: After initial power-up, the IC will ignore all logic inputs for a time period (T3-T1) of about:
6.4 x C SS T3 - T1 = ---------------------5
5V MAIN
5V Dual "bump" 4.5V
S3#O
(1)
S3#I
where T3-T1 is in ms if CSS is in nF. At T2 (about 2/3 of the way from T1 to T3), the 3.3V-ALW LDO is in regulation. The 3.3V LDO's slew rate is limited by the discharge slope of CSS. If 3.3V MAIN has come up prior to this time, the 3.3V-ALW node will already be pre-charged through the body diode of Q5 (see Figure 1). T3 to T4: The IC will start VDDQ only if 5V MAIN is above its UVLO threshold (5V MAIN OK). Provided 5V MAIN is up before T3, the IC waits about 100s before initiating soft-start on VDDQ to allow CSS time to fully discharge. The IC is in "SLEEP" or S5 state when EN is low. In S5, only the 3.3V LDO is on. If the IC is in S5 at T4, CSS will be held to 0V. T4 to T5: After VDDQ is stablized (when CSS is at about 1.3V) an internal VDDQ OK is generated which will allow the 1.2V LDO and the VTT LDO to start. To ensure that the VDDQ output is not subjected to large transient currents during S3 to S0 transition, the VTT and 1.2V LDO slew rates are limited by the slew rate of the SS cap until the LDO is in regulation. In addition, the VTT regulator is current limited. After VDDQ OK becomes true, CSS will be held to 1.2V until S3#I goes high. S0 to S3: The system signals this transition by dropping the S3#I signal. When this occurs, S3#O goes low, and the 3.3V LDO turns on. The 1.2V LDO and the VTT LDO are turned off, and CSS is discharged to 2V. SBSW pulls low to turn on the P-Channel 5V DUAL switch. S3 to S0: The system signals this transition by raising the S3#I signal. S0 mode is not entered until 5V MAIN OK. Then the following occurs: S3#O releases SBSW pulls high to turn off the P-Channel switch The 3.3V LDO turns off The 1.2V LDO and the VTT LDO are turned on and, and CSS is allowed to charge up
Figure 4. S3 to S0 Transition: 5V DUAL
To eliminate the "bump", add delay to the 5V MAIN pin as shown below. The 5V MAIN pin on the FAN5068 does not supply power to the IC, it is only used to monitor the voltage level of the 5V MAIN supply, and therefore is a high impedance input.
RDLY
+5MAIN FROM ATX
5V MAIN C DLY
4
Figure 5. Adding Delay to 5V MAIN
Another method to eliminate the potential for this "bump" is to use the PWR_OK to drive the 5V MAIN pin. Some systems cannot tolerate the long delay for PWR_OK (>100ms) to assert, hence the solution in figure 5 may be preferrable. S5 to S3: During S5 to S3 transition, the IC will pull SBSW low with a 500nA current sink to limit inrush in Q4 if 5V MAIN is below its UVLO threshold. At that time, 5V DUAL is discharged. The limited gate drive controls the inrush current through Q4 as it charges C1 (capacitance on 5V Dual). Depending on the CGD of Q4, the current available from 5VSB, and the size of C1, C13 may be omitted.
C1 * 5 x 10 I Q4(INRUSH) = ----------------------------------C13 + C GD(Q4)
-7
(2)
If 5V MAIN is above its UVLO threshold, SBSW will be pulled down with an impedance of about 2K. VDDQ will not start until 5V MAIN OK is true.
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PRODUCT SPECIFICATION
FAN5068
V(UVLO)
5V SB
4V 3.8V
1V
VDDQ
3.3V LDO
T0
T1
T2
T3 T4
T5
Figure 6. Start-up Sequence into S0.
PWM Regulator
A PSPICE model and spreadsheet calculator are available for the VDDQ PWM regulator to select external components and verify loop stability. The topics covered below provide the explanation behind the calculations in the spreadsheet.
PWM Soft Start
When the PWM regulator is enabled the circuit will wait until the VDDQ IN pin is below 100mV to ensure that the soft-start cycle does not begin with a large residual voltage on the PWM regulator output. When the PWM regulator is disabled, 50 is turned on from VDDQ IN to PGND to discharge the output. The voltage at the positive input of the error amplifier is limited to VCSS which is charged with a 50A current source. Once CSS has charged to 0.9V, the output voltage will be in regulation. The time it takes SS to reach 0.9V is:
0.9 x C SS T 0.9 = ---------------------50
Setting the output voltage
The output voltage of the PWM regulator can be set in the range of 0.9V to 90% of its power input by an external resistor divider. The internal reference is 0.9V. The output is divided down by an external voltage divider to the FB pin (for example, R1 and R2 in Figure 1). There is also a 1A precision (5%) current sourced out of FB to ensure that if the pin is open, VDDQ will remain low. The output voltage therefore is:
V OUT - 0.9V 0.9V ----------- = -------------------------------- + 1A R1 R2
(4)
(3a)
where T0.9 is in ms if CSS is in nF. CSS charges another 400mV before the PWM regulator's latched faults are enabled. When CSS reaches 2.5V, the VTT and 1.2V LDO will begin their soft-start ramps. After the VTT and 1.2V LDO regulators are in regulation, PGOOD is then allowed to go HIGH (open). UVLO on VCC will discharge SS and reset the IC. To prevent large duty cycles and high currents during the beginning of the PWM soft-start, the input to the PWM comparator is also clamped by CSS. This clamping action has no practical effect on operation of the circuit after CSS has passed about 0.4V.
To minimize noise pickup on this node, keep the resistor to GND (R2) below 2k. We selected R2 at 1.82k and solved for R1.
R2 * ( V OUT - 0.9 ) R1 = --------------------------------------------- = 1.816k 1.82k 0.9 - 1A
(3b)
The synchronous buck converter is optimized for 5V operation. The PWM modulator uses an average current mode control for simplified feedback loop compensation.
Oscillator
The oscillator frequency is 300kHz. The internal PWM ramp is reset on the rising clock edge.
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FAN5068
PRODUCT SPECIFICATION
COMP 1A FB ISS SS VREF ISNS + - + E/A 4.41K + RAMP
- + PWM
Figure 7. SS Clamp and FB Open Protection
S/H
COMP FB 4.41K V to I
in + ISNS TO PWM COMP ISNS
ISNS
RSENSE
LDRV in - PGND
SS/EN CSS
Reference and Soft Start
ILIM det.
2.5V I2 = ILIM*9.6 0.9V ILIM mirror ILIM R ILIM
Figure 8. Current Limit / Summing Circuits
Current Processing Section
The following discussion refers to Figure 8. The current through RSENSE resistor (ISNS) is sampled shortly after Q2 is turned on. That current is held, and summed with the output of the error amplifier. This effectively creates a current mode control loop. RSENSE sets the gain in the current feedback loop. For stable operation, the voltage induced by the current feedback at the PWM comparator input should be set to 30% of the ramp amplitude at maximum load currrent and line voltage. The following expression estimates the recommended value of RSENSE as a function of the maximum load current (ILOAD(MAX)) and the value of the MOSFET's RDS(ON).:
I LOAD ( MAX ) * R DS ( ON ) * 4.1k R SENSE = --------------------------------------------------------------------------- - 100 30% * 0.125 * V IN ( MAX )
Setting the Current Limit
An ISNS is compared to the current established when a 0.9 V internal reference drives the ILIM pin. RILIM, the RDS(ON) of Q2, and RSENSE determine the current limit:
( 100 + R SENSE ) 9.6 R ILIM = --------------- x --------------------------------------R DS ( ON ) I LIMIT
(7)
(5)
RSENSE must, however, be kept higher than:
I LOAD ( MAX ) * R DS ( ON R SENSE ( MIN ) = ----------------------------------------------------------) - 100 150A
(6)
Where ILIMIT is the peak inductor current. Since the tolerance on the current limit is largely dependent on the ratio of the external resistors it is fairly accurate if the voltage drop on the Switching Node side of RSENSE is an accurate representation of the load current. When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS. This value not only varies from device to device, but also has a typical junction temperature coefficient of about 0.4%/C (consult the MOSFET datasheet for actual values), so the actual current limit set point will decrease propotional to increasing MOSFET die temperature. A factor of 1.6 in the current limit setpoint should compensate for all MOSFET RDS(ON) variations, assuming the MOSFET's heat sinking will keep its operating die temperature below 125C.
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PRODUCT SPECIFICATION
FAN5068
COMP
Q2 LDRV ISNS RSENSE
C1 C2 R3 R1 VREF FB R2 C3
R1 PGND
VDDQ R4
Figure 9. Improving Current Sensing Accuracy
Figure 10. Compensation Network
More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET as shown in Figure 9. This approach causes higher losses, but yields greater accuracy. R1 is a low value (e.g. 10m) resistor. Current limit (ILIMIT) should be set sufficiently high as to allow inductor current to rise in response to an output load transient. Typically, a factor of 1.3 is sufficient. In addition, since ILIMIT is a peak current cut-off value, we will need to multiply ILOAD(MAX) by the inductor ripple current (we'll use 20%). ILIMIT > ILOAD(MAX) * 1.6 * 1.3 * 1.2 (8)
Figure 10 shows a complete type 3 compensation network. A type 2 compensation configuration eliminates R4 and C3 and is shown in Figure 1. Since the FAN5068 architecture employs summing current mode, type 2 compensation can be used for most applications. For critical applications that require wide loop-bandwidth, and use very low ESR output capacitors, type 3 compensation may be required. The PSPICE model and spreadsheet calculator can be used to calculate these component values.
PGOOD Signal
PGOOD monitors the status of the PWM output as well as the VTT and 1.2V LDO regulators. PGOOD remains low unless all of the conditions below are met: 1. 2. 3. 4. 5. S3#I is HIGH SS is above 4V Fault latch is cleared FB is between 90% and 110% of VREF VTT and LDO 1.2 are in regulation
Gate Driver Section
The Adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-tosource voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-tosource voltage of the upper MOSFET has decreased to less than approximately 1 volt. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1 volt. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to work properly. Any delay along that path will subtract from the delay generated by the adaptive dead-time circit and shoot-through may occur.
Protection
The converter output is monitored and protected against extreme overload, short circuit, over-voltage and under-voltage conditions. An internal "Fault Latch" is set for any fault intended to shut down the IC. When the "Fault Latch" is set, the IC will discharge VOUT by driving LDRV high until VDDQ IN < 0.5V. LDRV will then go low until VDDQ IN > 0.8V. This behavior will discharge the output without causing undershoot (negative output voltage). To discharge the output capacitors, a 50 load resistor is switched in from VDDQ IN to PGND whenever the IC is in fault condition, or when EN is low. After a latched fault, operation can be restored by recycling power or by toggling the EN pin.
Frequency Loop Compensation
The loop is compensated using a feedback network around the error amplifier, which is a voltage output op amp.
Under-Voltage Shutdown
If FB stays below the under-voltage threshold for 2s, the "Fault latch" is set. This fault is prevented from setting the fault latch during PWM soft-start (SS < 1.3V).
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PRODUCT SPECIFICATION
Over-Current Sensing
If the circuit's current limit signal ("ILIM det" as shown in Figure 8) is high at the beginning of a clock cycle, a pulseskipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next 8 clock cycles. If at any time from the 9th to the 16th clock cycle, the "ILIM det" is again reached, the fault latch is set. If "ILIM det" does not occur between cycle 9 and 16, normal operation is restored and the over-current circuit resets itself. This fault is prevented from setting the fault latch during soft-start (SS < 1.3V).
Over-Temperature Protection
The chip incorporates an over temperature protection circuit that shuts the chip down when a die temperature of about 160C is reached. Normal operation is restored at when the die temperature falls below 125C with internal Power On Reset asserted, resulting in a full soft-start cycle. To accomplish this, the over-temperature comparator should discharge the SS pin.
VTT Regulator Section (Figure 3)
The VTT regulator includes an internal resistor divider (50k for each resistor) from the output of the PWM regulator. If the REF IN pin is left open, the divider will produce a voltage that is 50% of VDDQ IN. The VTT regulator is enabled when S3#I is HIGH and the PWM regulator's internal PGOOD signal is true. The VTT regulator also includes its own PGOOD signal which is high when VTT SNS > 90% of REF IN.
PGOOD 1 IL SHUTDOWN 2 VOUT 8 CLK
LDO Controller
The LDO controller is typically used to provide 1.2V for the Front-side bus GTL termination. Drop-out voltage for this regulator will depend on the RDS(ON) of the external N-Channel MOSFET pass element that is selected. Gate drive comes from VCC and can pull up to within 0.5V of VCC line. With 1.2V output, the enhancement voltage for the MOSFET is: VENH = 4.75 - 0.5 - 1.2 = 3.05V. Therefore, a low enhancement voltage MOSFET should be used for the pass element. The LDO controller contains a soft-start circuit which limits its output slew rate when it powers up. The LDO's output voltage (V1.2) is established with the following equation (reference designators are from Figure 1.):
R7 V 1.2 = 0.9 x 1 + ------ R8
3 CH1 5.0V CH3 2.0A CH2 100mV M 10.0s
Figure 11. Over-Current Protection Waveforms
OVP / HS Fault / FB short to GND detection:
A HS Fault is detected when there is more than 0.5V from SW to PGND 350ns after LDRV reaches 4V (same time as the current sampling time). OVP Fault Detection occurs if FB > 115% VREF for 16 clock cycles. During soft-start, the output voltage could potentially "run away" if either the FB pin is shorted to GND or R1 is open. This fault will be detected if the following condition persists for more than 14 s during soft-start. 1. 2. VDDQ IN (PWM output voltage) > 1V and FB < 100mV
(9)
Design and Component Selection Guidelines
The spreadsheet calculator, which is part of AN-6006 can be used to calculate all external component values for the FAN5068. As an initial step, define: 1. 2. 3. 4. 5. Output voltage Maximum VDDQ load current Maximum load transient current and maximum allowable output drop during load transient RDS(ON) of the low-side MOSFET (Q2) Maximum allowable output ripple
Any of these 3 faults will set the fault latch. These 3 faults can set the fault latch during the SS time (SS < 1.3V). To ensure that FB pin open will not cause a destructive condition, a 1A current source ensures that the FB pin will be high if open. This will cause the regulator to keep the output low, and eventually result in an Under-voltage fault shutdown (after PWM SS complete).
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PRODUCT SPECIFICATION
FAN5068
Power MOSFET Selection
For a complete treatment of MOSFET selection and efficiency calculations, see: AN-6005: Synchronous buck MOSFET loss calculations with Excel model. Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND) losses. In typical applications, the FAN5068 converter's output voltage is low with respect to its input voltage, therefore the Lower MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should be therefore be selected to minimize conduction losses, thereby selecting a MOSFET with low RDS(ON). In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, and its conduction loss will therefore have less of an impact. Q1, however, sees most of the switching losses, so Q1's primary selection criteria should be gate charge.
The driver's impedance and CISS determine t2 while t3's period is controlled by the driver's impedance and QGD. Since most of tS occurs when VGS = VSP we can use a constant current assumption for the driver to simplify the calculation of tS:
CISS VDS
C GD
C ISS
ID
QGS Q GD
4.5V
VSP VTH
High-Side Losses:
Figure 12 shows a MOSFET's switching interval, with the upper graph being the voltage and current on the Drain to Source and the lower graph detailing VGS vs. time with a constant current charging the gate. The x-axis therefore is also representative of gate charge (QG). CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from MOSFET datasheets. Assuming switching losses are about the same for both the rising edge and falling edge, Q1's switching losses, occur during the shaded time when the MOSFET has voltage across it and current through it. These losses are given by:
P UPPER = P SW + P COND V DS x I L P SW = --------------------- x 2 x t S F SW 2 P COND V OUT 2 = -------------- x I OUT x R DS ( ON ) V IN
V GS
t1 t2
QG(SW)
t3 t4 t5
Figure 12. Switching Losses and QG
5V C GD RD HDRV RGATE G CGS SW
VIN
Figure 13. Drive Equivalent Circuit
Q G ( SW ) Q G ( SW ) t S = -------------------- ---------------------------------------------------I DRIVER VCC - V SP --------------------------------------------- R DRIVER + R GATE
(11)
(10a) (10b) Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS - QTH where QTH is the gate charge required to get the MOSFET to it's threshold (VTH). For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should also be taken to include the delivery of the MOSFET's gate power (PGATE) in calculating the power dissipation required for the FAN5068:
P GATE = Q G x VCC x F SW
where: PUPPER is the upper MOSFET's total losses, and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time) and is t2+t3 (Figure 12).
(12)
where QG is the total gate charge to reach VCC.
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PRODUCT SPECIFICATION
Low-Side Losses
Q2, however, switches on or off with its parallel shottky diode conducting, therefore VDS 0.5V. Since PSW is proportional to VDS, Q2's switching losses are negligible and we can select Q2 based on RDS(ON) only. Conduction losses for Q2 are given by:
P COND = ( 1 - D ) x I OUT x R DS ( ON )
2
PCB Layout General Guidelines
Switching converters, even during normal operation, produce short pulses of current which could cause substantial ringing and be a source of EMI if layout constrains are not observed. There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rate and are noise generators. The low power components responsible for bias and feedback functions are sensitive to noise. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Notice all the nodes that are subjected to high dV/dt voltage swing such as SW, HDRV and LDRV, for example. All surrounding circuitry will tend to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A. Minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components like the soft-start capacitor and current sense resistors as close as possible to the respective pins of the IC.
(13)
where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and
V OUT D = -------------V IN
is the minimum duty cycle for the converter. Since DMIN < 20% for portable computers, (1-D) 1 produces a conservative result, further simplifying the calculation. The maximum power dissipation (PD(MAX)) is a function of the maximum allowable die temperature of the low-side MOSFET, the J-A, and the maximum allowable ambient temperature rise:
T J ( MAX ) - T A ( MAX P D ( MAX ) = -------------------------------------------------) J - A
(14)
J-A, depends primarily on the amount of PCB area that can be devoted to heat sinking (see FSC app note AN-1029 for SO-8 MOSFET thermal information).
PCB Design Guidelines:
Below is a summary of recommendations for PCB layout when using MLP packages: 1. PCB lead finger pad should be designed 0.2-0.5mm longer than the package terminal length for good filleting. Non Solder Mask Defined (NSMD) pads are recommended over SMD pads due to the tighter tolerance on copper etching than solder masking. For Good thermal performance it is recommended to use 4 layer PCB's with vias to effectively remove heat from the device. For a 5X5 die size, it is recommended to use 0.30.33mm size holes in the middle. Vias should be plugged to prevent voids being formed between the exposed pad and PCB thermal pad due to solder escaping by the capillary effect. This can be avoided by tenting the via during the solder mask process. The via solder mask diameter should be 100m larger than the via hole diameter.
Specific Layout recommendations
All component designators reference Figure 1. Layout examples refer to the FAN5068 EVAL board, available through your Fairchild Semiconductor representative. 1. All currents flow in a closed path. All routing should ensure that the currents are returned to their source of origin by the shortest possible path without creating unnecessary loops. A Multi layer (4 layers or more) PCB facilitates the use of a complete Ground layer which acts as very low impedance return path for both the control and power return currents. This ground plane will also increase the noise immunity of the control circuit by providing a shield against radiated disturbances. In the Eval board layout Layer 2 is reserved for the GND plane. VCC of the controller should be de-coupled with a ceramic capacitor (C4) very close to the pin. If it is possible, the capacitor could be connected across the VCC (#14) and the GND (#19) pins on top copper. Pin 19 should also connect to the GND plane with a via at the pin. If a short top-copper connection for C4 is not possible the capacitor should be close to the VCC pin with 15
2.
3.
2.
4. 5.
3.
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PRODUCT SPECIFICATION
FAN5068
the other side connected to the ground plane through a via. If there is a significant amount of noise on VCC pin, L-C decoupling at the VCC pin can be used to attenuate the noise. 4. The pad under the IC is for power ground return. This pad needs to be directly connected to the ground plane by vias under the IC as mentioned above. Do not connect this pad to Pin #19 through the top copper, as this is the analog ground at the IC.
plane as close to pin 19 as possible and away from other current on the GND plane.
The Loop around C19,R11 and R1,R2 is minimized
8. 9.
This is the Decoupling Capacitor Close to VCC Pin
Minimize the path length for the boot cap formed by SW, C5 and pin 8. Use thick trace widths for Q1 and Q2 gate drive signals to minimize their resistance and inductances. Top copper should be used to route the gate drive traces if possible, especially Q1 Gate to HDRV.
This is the Ground Pin
These are the 5 holes below the IC for easy flow soldering
10. Power Plane Routing: The Power Plane routing for traces carrying higher currents as in the VDDQ output, need to be routed carefully. The loop from C2 (5V Dual high frequency bypass cap) to the source of Q2 needs to be minimized to minimize ringing on SW and Q1 drain. The loop formed by COUT to the source of the Q2 also needs to be minimized to keep the ringing on the switch node low. Basically what we are trying to achieve by doing this is to reduce the loop inductance and thereby minimizing the energy in the stray inductance.
Q1
C13
5. 6.
Use copper planes for power and GND wherever possible to reduce trace resistance and inductance as well. Resistors should be as close to the IC pins as possible to prevent noise pickup due to radiated and adjacent high dV/dT signals. Avoid routing sense signals near the gate drive, SW node, boot, or other high dV/dT nodes. Particular care should be taken to place R3 (ISNS resistor) as close as possible to pin 11
R5 is very close to ILIM pin R3 is very close to ISNS pin
C14
Q2
C16 L1
C20
The Loop around C6,R6 and C9 is minimized
- Q1 ON time Current flow path - Q2 ON time Current flow path
7.
The closed path (loop) around the feedback components should be minimized to avoid noise pickup. These components will need to be close to the feedback pin. R2, R10 and C10 should be returned to pin 19 or to the GND
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FAN5068
PRODUCT SPECIFICATION
Dimensional Outline Drawing
0.15 C 2X 5.0 A B 24 3.25 19
1
18
5.50 5.0 3.25 3.91 6 (0.79) 0.15 C TOP VIEW 2X 7 0.65 TYP 12 0.42 TYP
13
0.80 MAX 0.10 C (0.20) 0.08 C 0.05
0.00 SEATING PLANE
RECOMMENDED LAND PATTERN
C SIDE VIEW 3.25 7 12 13
0.45 0.35
6
3.25 0.65 1 PIN #1 IDNET 24 0.65 19 0.25~0.35 0.10 M C A B 0.05 M C
18
BOTTOM VIEW Notes: A) Conforms to JEDEC registration number MO-220, variation WHHC, dated Aug/2002. B) Dimensions are in millimeters. C) Dimensions and tolerances per asme Y14.5-1994.
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PRODUCT SPECIFICATION
FAN5068
Ordering Information
Part Number FAN5068MPX Temperature Range -10C to 85C Package MLP-24 5x5 mm Packing Tape and Reel
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9/9/04 0.0m 004 Stock#DS30005068 2004 Fairchild Semiconductor Corporation

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